1. Field of the Invention
The present invention relates generally to bipolar transistor logic circuits, and more particularly, to emitter coupled logic (ECL) and non-threshold logic (NTL) circuits wherein the dc power dissipation and switching current are greatly reduced by utilizing an ac-coupled complementary push-pull output stage.
2. Description of the Prior Art
The design of high-speed bipolar circuits is often a compromise between speed, power consumption, and current drive capability. Faster switching speeds can be achieved at the expense of higher power dissipation and a larger switch current, and lower power dissipation can be achieved but at the expense of slower switching speeds. For example, FIG. 1 is a schematic diagram of a conventional ECL circuit 1. The input signal is applied to the bases of transistors 2 and 3 which are differentially coupled to transistor 4. Since the output is taken from node A, the output will perform a NOR function of the input signals. The base of transistor 4 is tied to a reference voltage V.sub.REF which is equal to the median between the logical high voltage and the logical low voltage of the integrated circuit 1. Transistor 5 and resistor 9 provide a current source for differential transistors 2, 3 and 4.
When the input signal to the base of transistor 3 is a logical low voltage, transistor 3 is off, and transistor 4 is on. The current provided by transistor 5 and resistor 9 flows through transistor 4. The voltage at node A is high. The output is taken from node A through transistor 6 which is connected in an emitter follower configuration. Thus, the output will be a high output voltage. When the input rises from a logical low voltage to a logical high voltage, transistor 3 will switch on and transistor 4 will switch off once the input signal crosses V.sub.REF. As transistor 3 switches on, node A will fall from a high voltage to a low voltage pulling the base of transistor 6 low and providing a low output voltage. The output is pulled down from a high output voltage to a low output voltage through resistor 10 to discharge the load capacitor C.sub.L. Load capacitor C.sub.L consists of the capacitances of any driven gates and wiring capacitance. The time required to pull down the output is determined by the time required for the input signal to rise from a logical low voltage to V.sub.REF, the time required to pull down the voltage at node A, and the time needed to discharge capacitor C.sub.L from a high output voltage to a low output voltage through resistor 10. The latter time is determined by a time constant which is obtained by multiplying the resistance of resistor 10 by the capacitance of capacitor C.sub.L. Thus, in order to achieve a fast pull-down, resistor 10 must be as low as possible. However, this results in a higher dc current I.sub.EF and, thus, higher power dissipation. In addition, the dc current I.sub.EF during stand-by and during switching is the same which results in high dc power dissipation.
When the input switches from a logical high voltage to a logical low voltage, transistor 3 will switch off, and transistor 4 will switch on. The base of transistor 6 is pulled high through resistor 7 thereby turning transistor 6 on strongly to charge the output node and provide a high output voltage. ECL circuit 1 is limited in its operation when pulling up the output by the need to provide the drive current for transistor 6 through resistor 7. ECL circuit 1 is further limited in that the switching current I.sub.CS is the same whether it is flowing through resistor 7 and transistor 3 or through resistor 8 and transistor 4 because the current source, transistor 5 and and resistor 9, supplies the same I.sub.CS regardless of which differential transistor is on. Thus, resistor 7 and resistor 8 have the same resistance values. The time required to pull up the output is determined by the time required for the input signal to fall from a logical high voltage to V.sub.REF, the time required to pull up the voltage at node A through resistor 7 which determines the time needed to charge capacitor C.sub.L from a low output voltage to a high output voltage through emitter follower transistor 6. Therefore, in order to achieve a fast pull-up of the voltage at node A, resistor 7, and thus resistor 8, must be selected as low as possible. However, the switching current I.sub.CS is inversely proportional to resistors 7 and 8 for a fixed voltage swing. Thus, a small value for resistors 7 and 8 will result in a large switching current I.sub.CS.
As described above, there are two problems with high speed conventional ECL circuits: (1) the pull-down delay is limited by resistor 10. Thus, high speed operation means a small resistor value for resistor 10 and high dc current I.sub.EF. (2) The pull-up delay is limited by resistors 7 and 8. Thus, a fast pull-up means small resistors 7 and 8 and a large switch current I.sub.CS.
A circuit which has been developed to overcome the first problem in ECL circuit 1 is described in C.K. Chuang and K.Y Toh, "High-Speed ECL Circuit," Vol. 32 No. 4A IBM Tech. Discl. Bull. 374-380 (1989). This circuit reduces the dc power dissipation by implementing a low power ac-coupled active pull-down (APD) emitter follower output stage. In the APD-ECL, resistor 10 is replaced by an NPN pull-down transistor with a collector connected to the output node, an emitter returned to V.sub.EE and a base ac-coupled through a capacitor to the collector of transistor 4.
In the APD-ECL circuit, the base of the pull-down transistor is biased to maintain a low steady state current. As in conventional ECL circuit 1, when the input signal rises from a logical low voltage to a logical high voltage, node A will fall from a high voltage level to a low voltage level and emitter follower transistor 6 is cutoff. At the same time the voltage at the collector of transistor 4 rises from a low voltage level to a high voltage level, and this signal is ac-coupled to the base of the pull-down transistor. The coupling capacitor couples a transient voltage pulse to the base of the pull-down transistor, thereby turning on the pull-down transistor strongly and briefly to provide a large transient pull-down current. Thus, a small emitter follower current I.sub.EF can be used while still maintaining a fast pull-down. The pull-up transistor is turned off momentarily, thus, further improving the pull-down delay.
The APD-ECL is faster, and the output transition from a high output voltage to a low output voltage is steeper than the discharge through resistor 10 in conventional ECL circuit 1. This is because the current used to discharge capacitor C.sub.L is supplied by the pull-down transistor which has a much smaller time constant than the passive pull-down in circuit 1. The power dissipation in the emitter follower stage of the APD-ECL is much less than that of circuit 1 because the dc current in the output stage is small during stand-by and momentarily raised up during switching, whereas in circuit 1, I.sub.EF is at the same value during stand-by and when circuit 1 switches. A secondary advantage of the APD-ECL circuit stems from the fact that the steady state current through the emitter follower transistor 6 is low, and therefore, the output high voltage is approximately 100 mV closer to V.sub.CC than in conventional ECL circuit 1. Thus, a lower V.sub.CC may be used which further reduces the dc power dissipation in the APD-ECL circuit.
Although the APD-ECL circuit is an improvement over conventional ECL circuit 1, the former circuit does not overcome the second problem stated above. A large switching current I.sub.CS is still necessary to achieve fast switching of the logic stage, especially for the pull-up which is still limited by pull-up resistors 7 and 8.
FIG. 2 is a schematic diagram of a conventional non-threshold logic (NTL) circuit 11. The operation and power/speed performance of conventional NTL circuit 11 is similar to that described above for ECL circuit 1 except for the differences discussed below. In NTL circuit 11 there is no reference transistor differentially coupled to the input transistors 12 and 13, and as a result, the voltage at the base of the emitter follower transistor 14 will immediately rise or fall when the input falls or rises. Thus, the delay component in ECL circuit 1 attributable to the time it takes for the input signal to rise to V.sub.REF during pull-up, is not present in NTL circuit 11. In addition, because no reference voltage is required, NTL circuit can be operated with a lower power supply than conventional ECL circuit 1, and therefore, dissipates less dc power than ECL circuit 1.
The two problems present in ECL circuit 1 are also present in conventional NTL circuit 1: (1) the pull-down delay is limited by resistor 18. Thus, high speed operation means a small resistor value for resistor 18 and high dc current I.sub.EF. (2) The pull-up delay is limited by pull-up resistor 15. Thus, a fast pull-up means a small pull-up resistor 15 and a large switch current I.sub.CS.
A circuit which has been developed to overcome the first problem in NTL circuit 1 is described in M. Usami and N. Shiozawa, "SPL (Super Push-Pull Logic) A Bipolar Novel Low-Power High-Speed Logic Circuit," Dig. of Tech. Papers, Symp. on VLSI Cirs., 11-12, May, 1989. The SPL circuit is similar in operation to the APD-ECL in that the SPL circuit reduces dc power dissipation by utilizing an ac-coupled active pull-down transistor. In the SPL circuit the base of a pull-down transistor is ac-coupled to the emitter(s) of the input transistors via a capacitor. The collector of the pull-down transistor is coupled to the emitter of the output emitter follower transistor 14 and to the output node and the emitter of the pull-down transistor is returned to V.sub.EE. The capacitor couples a transient voltage pulse to the base of the pull-down transistor, thereby turning on the pull-down transistor providing a large transient pull-down current. However, the SPL circuit does not overcome the second problem stated above. A large switching current I.sub.CS is still necessary to achieve fast switching of the logic stage, especially for the pull-up which is still limited by pull-up resistor 15.